Regulation method for the source terminal voltage in a non-volatile memory cell during a program phase and corresponding program circuit

ABSTRACT

A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for locally regulatingthe source terminal voltage in a non-volatile memory cell during thecell programming and/or reading phases. More particularly, the inventionrelates to a method for locally regulating the source terminal voltagein a non-volatile memory cell during the cell programming and/or readingphases, wherein the voltage is applied by a program-load circuitconnected in a conduction path used for transferring a predeterminedvoltage value to at least one terminal of the memory cell. The inventionfurther relates to a program-load circuit which is incorporated in anelectronic semiconductor-integrated memory device comprising an array ofnon-volatile memory cells, with each of the cells including at least onefloating gate transistor having source, drain, gate, and body terminals,and each program-load circuit being connected in a conduction path usedfor transferring a predetermined voltage value to a terminal of thememory cell.

BACKGROUND OF THE INVENTION

[0002] As it is well known in this field of application, a pressingdemand for high-density non-volatile memory semiconductors, e.g. flashEEPROMs, from a world-wide semiconductor market has lead to the studyand the application of the so-called multi-level memory devices, whereineach memory cell can store more than one bit. Each bit is associatedwith a predetermined logic level, and the logic levels can be recognizedby memory cells having several threshold voltages.

[0003] The skilled persons in the art will appreciate that an increasednumber of threshold voltage levels places stricter demands on theoperations to be carried out on the cells, viz. the cell erasing,programming, and reading operations. Reliability considerations placethe assigned range reserved for the 2^(n)-1 distributions (all of themexcept for the most programmed one) of a multi-level non-volatile memorycell having n bits/cell at less than 4.5-5V. Consequently, both thewidth of the threshold distributions and their separation margins becomesmaller. FIG. 1 of the accompanying drawings is a comparative plot ofthe threshold voltage distribution in a conventional two-level (two bitsper cell) memory cell and in a multi-level memory with three bits percell.

[0004] As a result, a series of phenomena are faced during thefabrication of multi-level memory devices that would be of trivialimport for conventional two-level memories. To make the aspects of thisinvention more clearly understood, the phases for programmingmulti-level flash memories will be reviewed here below.

[0005] A flash cell read operation includes varying the thresholdvoltage of the cell by a desired amount. This is achieved by a build-upof electrons in the floating gate region. Shown in FIG. 2 are somestraight lines that represent the characteristic relation of the voltageapplied to the gate terminal of a memory cell with the threshold skipthat results from varying the voltages applied to the drain terminal ofthe cell.

[0006] To program the cell and obtain threshold voltage distributionswith sufficient precision to yield the multi-level feature, the voltageapplied to the control gate terminal may be varied stepwise from aminimum to a maximum value. Under optimum gate terminal conditions, thewidth of each voltage step is equal to the threshold skip sought.

[0007] The use of a stepwise gate voltage brings about a timing problem,if the program operation is to be completed in an effective manner. Alarge number of cells should be programmed in parallel, to minimizeprogram time. Parallel programming is implemented by an algorithm,called “program & verify”, in the course of whose execution each programpulse is followed by a step of reading the cells being programmed tocheck if they did or did not attain the threshold value.

[0008] Any programming pulses will be delivered to properly programmedcells, while cells that have not reached a desired threshold yet will bere-programmed using the same algorithm. Program-load circuits are usedfor this purpose that allow predetermined program voltage values to beselectively applied to the drain terminals of cells to be programmed. Atthe same time, the voltage to be applied to the source terminal shouldbe accurately controlled during both the programming and the readingstep.

[0009] It has been common practice to connect the cell sources to groundduring the programming and reading phases by using a predeterminednumber of pass transistors, usually of the n-channel type. FIG. 3 showsan array sector 11 having four pass transistors 16 placed at each sectorapex and individually driven by a SRCCON signal.

[0010] The reason for having a ground connection established throughpass transistors is that the cell source terminals, to which a varyingpositive voltage can be applied during the erasing phase, should not beconstantly left connected to ground. During the programming phase, thevalue of the source voltage undergoes modulation due to the parasiticresistances of the lines and the pass transistors through which thesource is taken to ground, as do the voltages to the drain and bodyterminals of the memory cells. This results in the effectiveness of thepulses that vary with the number of cells to be programmed. In addition,the source voltage thus modulated has a drawback in that it affects thedrain-source V_(DS) and body-source V_(BS) voltage drops, and especiallythe gate-source V_(GS) voltage drop with attendant overdrive.

[0011] The effects of source voltage modulation also occur during theverifying and reading operations. The outcome of a modulated sourcevoltage is illustrated by the graph of FIG. 4 showing a sequence ofvoltage-current characteristics of a generic array cell. Characteristic(1) will be considered first. For the cells to be regarded as erased,they must have a larger current than the one of the reference EV (eraseverify) as to their gates is applied a voltage V_(READ). Under thiscondition, a large current is injected through the source terminal S,resulting in the characteristic portion for the largest currents takinga bend. Since the condition to be verified is a current, it can only bemet by keeping the cell threshold voltages slightly below those of thecell EV. Characteristic (1) is that of a generic cell, such as i-thcell.

[0012] As to characteristic (2), let us assume that the write buffercontaining the i-th cell is to be programmed with a pattern where allthe cells are at the distribution with less current (i.e. a “00”distribution, past the reference cell PV3), with the exception of thei-th cell which is programmed for the second distribution (“10”distribution, past the reference cell PV1). Since during the programmingstep the cells progress approximately at the same rate, characteristic(2) for the i-th cell can be taken to be similar to that of the othercells. Here again the characteristic shows a bend due to the injectionthrough the source terminal still being quite high, although lower ifcompared to the first characteristic. The i-th cell is verified to havebeen programmed at the desired distribution, and is then disconnectedfrom its program-load circuit, whereas the other cells keep receivingpulses until the desired threshold is reached.

[0013] As regards characteristic (3), all the cells have attained theirdesired distributions and are read. The injection through the sourceterminal will be quite moderate because the thresholds of all the cellsbut the i-th lie above the read voltage. Therefore, the characteristicof the i-th cell will no longer show a bend in the large-current range.Thus, if no additional margin has been considered for source voltagemodulation, the sense amplifier may erroneously read (or verify) thei-th cell.

[0014] The above is just a simple qualitative example of how heavily themodulation of the source voltage may be felt, and of how the method ofthis invention can make this modulation a constant one for each cell,irrespective of the charge state of the other cells with which it isread or verified, especially if the target is a multi-level cell arrayhaving more than two bits per cell.

SUMMARY OF THE INVENTION

[0015] An object of the invention is to provide a method for regulatingthe voltage applied to the source terminal of a non-volatile andmulti-level memory cell during the programming and/or reading phases,which method has adequate functional features such as to significantlyreduce the effects of the voltage modulations due to parasiticresistances at the connections between the supply voltage sources andthe circuit portions which are to receive such a supply.

[0016] The invention causes a local regulation of the source voltage bycomparing the current Is that flows through the source S of the arraycells with a suitable reference current Iref. If the current Is thatflows through the source terminal S is smaller than the referencecurrent Iref, a suitable driven current generator will inject currentinto the source terminal S until the array current values equal thereference current ones.

[0017] Based on this idea, the technical problem is solved by a methodas indicated, and as defined in claim 1 hereto.

[0018] The technical problem is further solved by a program-load circuitas defined in claim 6 foll.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The features and advantages of the method and the circuitaccording to the invention should become apparent from the followingdescription of embodiments thereof, given by way of example and not oflimitation with reference to the accompanying drawings.

[0020]FIG. 1 schematically shows a comparative plot of the thresholdvoltage distribution in a conventional two-level memory cells with twobits per cell and in a multi-level memory with three bits per cell.

[0021]FIG. 2 shows, in a voltage vs. voltage plot, certaincharacteristic curves of a multi-level memory cell of the prior art.

[0022]FIG. 3 schematically shows a sector of a memory cell array in anelectronic non-volatile memory device, having pass transistorsassociated therewith to connect the source terminals of the cells toground as in the prior art.

[0023]FIG. 4 shows a plot of a series of three voltage vs. currentcharacteristic curves for memory cells that undergo differentmodulations of the source voltage as in the prior art.

[0024]FIG. 5 schematically shows a circuit portion of the presentinvention operative to generate a voltage Vmat which is proportional tothe source current of the memory cells.

[0025]FIG. 6 schematically shows a circuit portion operative to generatea reference voltage Vref.

[0026]FIG. 7 shows an example of a comparison between the voltagesgenerated by the circuit portions of FIGS. 5 and 6.

[0027]FIG. 8 schematically shows an improved part of the example in FIG.5.

[0028]FIG. 9 schematically shows a modified embodiment of the example inFIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] With reference to the drawings, in particular to the embodimentsshown in FIGS. 5 to 9, a source voltage regulating circuit embodyingthis invention is generally shown at 1 in schematic form. The circuit 1is useful in an electronic memory device to locally regulate themodulation of the source voltage of the non-volatile memory cells 3during the cell programming and/or reading phases. Memory device is heremeant any monolithic electronic device incorporating an array of memorycells laid into rows and columns, as well as circuit portions that areassociated with the cell array to serve functions of addressing,decoding, reading, writing, and erasing the contents of the memorycells. A device as above may be, for instance, asemiconductor-integrated memory chip of the non-volatile flash EEPROMtype, which is split into sectors and can be electrically erased.

[0030] Each memory cell comprises a floating gate transistor havingsource S, drain D, and control gate G terminals. Between the circuitportions that are associated with the cell array there intervene theregulating circuit 1 and program-load circuits that are individuallysupplied by a specified supply voltage. This voltage is generatedinternally of the integrated memory circuit and regulated by a drainvoltage regulator.

[0031] The teachings of this invention are put to use specifically toeffect a local regulation by the sector of the source voltage Vs, bothduring the programming and the reading phase. The voltage applied to thesource terminal S of the cells 3 is a parameter that should becontrolled with great accuracy during both the programming and thereading phase.

[0032] According to the invention, the source voltage is regulated bycomparing the current Is that flows through the source S of the arraywith a suitable reference current Iref, as schematically illustrated bythe schematic example of FIG. 5.

[0033] When the current Is that flows through the source terminal S issmaller than the reference current Iref, a suitable controlled currentgenerator 25 injects current into the source terminal S until the arraycurrent values equal the reference current ones. The value of thereference current Iref is equal to the largest current that can flowthrough the source S, viz. the current that produces the maximummodulation of the source voltage with respect to ground level. Noteshould be taken of that it matters less that the level of the sourcevoltage during the programming phase be identical to the one of thelevel during the reading or verifying phase than that said level be heldconstant throughout the programming algorithm and as the programmingpattern varies.

[0034] Let us see now in detail how the method indicated above can beimplemented. The embodiments of FIGS. 5 and 6 respectively comprise afirst circuit portion comprising a branch 22 where an array voltage Vmatis generated, and a second circuit portion having a branch 23 where areference voltage Vref is generated. Also provided are: a comparator 24arranged to compare the two voltages, and a driven current generator 25for stabilizing the source voltage, both components being illustrated inFIG. 7.

[0035] Let us assume first that the value of the drain current Id duringthe programming phase is not much different from the current draw of thecells located in the most erased of the distributions during the readingphase. This assumption is made plausible by that a multi-level flashcell located in the erased distribution exhibits on reading an averagedrain current of 70 μA. On the other hand, upon receiving a programmingpulse under applied voltages VDS=4V, VBS=1.2V and VGS=0.3V+Vth, thissame cell would exhibit a drain current of about 60 μA.

[0036] With reference to FIG. 5, the place of any one of the transistorsarranged as shown to connect the array source to ground is taken,according to the invention, by two transistors M4 and M5 such that:

(W/L)_(M4)=(n−1)(W/L)_(M5),

[0037] where n is the number of cells being programmed in parallel.

[0038] The selection signal Vmtsource to the gates of transistors M4 andM5, instead of being the same level as the device power supply, isgenerated by a suitable regulator, so that the contribution to sourcemodulation from variations of VDD can be reduced or eliminated. Byarranging for the signal Vmtsource to be a high-voltage signal (e.g.equal to the read gate voltage level), the full-load value to the sourcecan be decreased and the “modulation” effects reduced accordingly.

[0039] An operational amplifier OA2 compares the outgoing voltage fromtransistor M5 with the ground value. This amplifier has its output fedback to an input through a resistor R3. By reason of the virtual groundprovided by opamp OA2 being supplied between the positive supply VDD andthe negative supply Vneg, this transistor M5 will be in the same biascondition as transistor M4, and the following current passed through it:

ID _(M4)/(n−1)=(Vds _(M5))/Req _(M5)

[0040] Since the amplifier OA2 is an inverting configuration, its outputvoltage Vmat is given as:

Vmat=R 3*(−Vds _(M5))/Req _(M5),

[0041] i.e., proportional to a fraction of the current Is flowingthrough the source node.

[0042] Shown in FIG. 6 is the circuit portion where the referencevoltage Vref is generated. The current of a flash cell 3 in the mosterased distribution, as biased for the reading condition, is mirrored onthe branch 23 that includes transistors M2 and M3. Transistor M3 is thesame size as the transistor M5 shown in FIG. 5 and receives the signalVmtsource, with resistor R2 being the same value as R3, and opamp OA1identical with OA2. Similar as in the array branch 22, the voltage Vrefoutput from the opamp is given as:

Vref=R2*(−Vds _(M3))/Req _(M3),

[0043] i.e. is proportional to the current that is generated by anerased cell, which has a similar value to that of the drain current Idduring the programming step. This means that the voltage Vref will beproportional to the current flowing through M5 when all the cells areconnected to the program-load circuits 1.

[0044] The branch 23 further includes a circuit block comprising a logicgate NOR1 and a transistor M1 acting as a regulator for the drainvoltage, to prevent the soft writing that would result from continualapplication of excessively high voltages to the drain. In addition, thevoltage Vref is generated according to the flash memory cell 3, andallows variations in the cell gain and in the value of Req_(M3) to befollowed.

[0045]FIG. 7 shows a circuit 21 representing a combination of thecircuit portions of FIGS. 5 and 6, and allows the comparison between thevoltages Vmat and Vref, this taking place through the comparator 24 COMPbeing fed between the VDD and the negative voltage Vneg. When voltageVmat is lower than voltage Vref, that is, if a smaller current Is flowsthrough the source node than would flow if all the cells were connectedto their respective program-load circuits, the output of the comparator24 will force the controlled current IFORCE generator 25 to inject, intoa node MATRIX SOURCE, a current given as:

IFORCE=I,full load−I, measured

[0046] thus keeping the voltage to the node MATRIX SOURCE at a constantvalue.

[0047] This compensation method can be effectively used to verify theprogramming and erasing phases, when the current injected into thesource S is function of the programming pattern and the point reached bythe programming algorithm. However, the method is also useful to thereading step, when the current injected into the source is dependent ona pattern previously programmed in the cells.

[0048] During the reading and verifying phases, the largest current Isthat flows through the source S is equal to the largest current of thecells located in the most erased distribution multiplied by the numberof cells that are read or verified in parallel. This is, therefore, whatjustifies using a cell 3 that has been programmed to the level EV forthe purpose of generating the reference voltage. However, this is notalways true, since while the program pulse is being applied, forexample, the current would be dependent on the cell geometry and on thegate voltage step applied (as well as on the values of the drain,source, and body voltages).

[0049] There are two ways of obviating this further difficultly. A firstapproach is shown in FIG. 8, whereby the transistor linking the sourcenode to ground, viz. the connection provided by the parallel oftransistors M4 and M5 in FIG. 5, is split into a set of n elementarytransistors, where n is the number of cells that are programmed inparallel. The gates of these n transistors can be driven by signalsPLENi, which signals are the selection signals of the program-loadcircuits as possibly brought to a regulated voltage level for them notto be affected by the modulation due to variations of VDD, e.g. broughtto a high voltage level for lower resistivity of the individual passtransistors.

[0050] While programming pulses are being applied, a number of sourcepass transistors equal to the number of program-loads in operation, viz.the number of cells through which the program current is actuallyflowing, are connected in. In this way, the source line will be held ata constant value during the programming algorithm, while for theverifying and reading operations, the arrangements shown in FIGS. 5-7can still be used.

[0051] There is, however, another way of reducing or minimizing sourcevoltage modulation, which is just as effective. This approach would usethe arrangements of FIGS. 5-7 even when the level of the programmingcurrent considerably differs from that of the cells in the eraseddistribution. FIG. 9 shows a comprehensive arrangement that provides formultiple reference voltages to be used on the occasion during thosesteps where source voltage modulation is a factor.

[0052] Instead of the array cell 3 located in the distribution havingthe highest current level, a current generator 18 is employed which iscontrolled by appropriate control signals S_(0, . . . n), whereby thecurrent IMVP from the generator can be changed. In this way, one circuitcan be effectively used in any of the device operation modes, viz. theprogram, program verify, erase verify, and read modes, by merely varyingthe value of the current IMVP.

[0053] To summarize, the regulation method and circuit of this inventionallow the voltages to the source terminals of the memory cells to bestabilized during the steps of programming and reading multi-level flashmemories. By keeping the values of such voltages stable during theprogram operations, the invention described above enables the gatepulses applied during the programming algorithm to effectively produce aconstant threshold voltage skip at each pulse and with any programpatterns.

[0054] Furthermore, the method of stabilizing the source voltageaccording to the invention is also applicable to the verify operations,thereby to reduce the undefined portion from the sense amplifier due tothe source voltage modulation brought about by the verifying and readingsteps taking place under bias conditions unlike those of the cells.These are not conditions to be disregarded where flash memories that canstore two or more bits per cell are involved.

That which is claimed is:
 1. A method for regulating the source terminal(S) voltage in a non-volatile memory cell (3) during the cellprogramming and/or reading phases, characterized in that it comprises:comparing the source current (Is) of the cell array (3) with a referencecurrent (Iref); converting a fraction of the source current (Is) to avoltage; and comparing said voltage with a voltage generated from amemory cell acting as a reference and being programmed to thedistribution with the highest current levels; the comparison resultbeing used for controlling a current generator (25) to inject, into thesource terminal (S), a current as required to keep said predeterminedvoltage thereof at a constant value.
 2. A method according to claim 1,characterized in that said source current (Is) is compared with areference current (Iref) provided by a generator of a current that isvaried by n control signals (Si).
 3. A circuit (1) for regulating sourcevoltage (Vs), incorporated in an electronic semiconductor-integratedmemory device comprising an array of non-volatile memory cells (3)divided into sectors, with each said cell including at least onefloating gate transistor having source (S), drain (D), gate (G), andbody (B) terminals, said circuit being characterized in that itcomprises: a two-input comparator (24); an array circuit branch (22)connected to one comparator input and operative to generate an arrayvoltage (Vmat), said array voltage being proportional to at least afraction of the current (Is) flowing through the source terminal; asecond circuit branch (23) connected to another comparator input andoperative to generate a reference voltage (Vref), said reference voltagebeing proportional to the current generated by an erased cell; and acurrent generator (25) controlled by the comparator (24) output tostabilize said source voltage (Vs).
 4. A circuit according to claim 3,wherein said current generator (25) is controlled by control signalsS_(0, . . . , n) suitable to vary the current (IMVP) generated by saidcurrent generator.
 5. A circuit according to claim 3, wherein saidcurrent generator injects the source, during the reading step, with acurrent dependent on the pattern previously programmed into the cells.6. An electronic multi-level memory device of the flash EEPROM type,being monolithically integrated in a semiconductor and comprising anarray of non-volatile memory cells (3) divided into sectors, with everysaid cell including at least one floating gate transistor having source(S), drain (D), gate (G), and body (B) terminals, said device beingcharacterized in that it comprises a set of n source pass transistorsconnected between the apices of each sector and corresponding groundreferences, with n being selected according to the number of array cellsto be programmed.
 7. A device according to claim 6, characterized inthat the number of source pass transistors matches the number of activedrain program-loads.
 8. A device according to claim 6, characterized inthat said n pass transistors are driven by signals (PLENi) correspondingto selection signals of the program-load circuits.